cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 55

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
2.3.3.3 B2-1, B2-2, and
B2-3
The Line BIP-8 bytes, B2-1, B2-2, and B2-3, are used for line error monitoring.
Similar to the B1 byte in the Section Overhead, B2 also uses Bit Interleaved Parity
(BIP-24) code with even parity. It contains the result from the calculation of all
the bits of the line overhead and STS-1 envelope capacity of the previous STS-1
frame before scrambling.
Line BIP-8 calculation on each STS-1 line within the STS-3c/STM-1 section. The
Line BIP-8 is calculated for all the bits of the STS-1 line Overhead and Envelope
Capacity of the previous frame before scrambling. Thus, in an STS-3c/STM-1
signal, 3 bytes (B2-1, B2-2, and B2-3) are used for the error monitoring function.
accumulated in an 18-bit counter (B2CNTL, B2CNTM, B2CNTH; 0x50, 0x51,
0x52). The counter is latched so that it can continue counting while the latch is
being read. This prevents loss of any error counts.
corresponds to B2-1, bit 4 corresponds to B2-2, and bit 3 corresponds to B2-3.
One byte (either B2-1, B2-2, or B2-3) in the Line Overhead is allocated for a
As many as 192 k errors per second can be detected. The errors are
Errors can be inserted via register ERRINS (0x06), bits 5, 4, and 3. Bit 5
Mindspeed Technologies
2.3 SONET/SDH Framer and Overhead Processor
™
2.0 Functional Description
2-19