cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 24

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

1.0 Product Description
1.4 CX28250 Pinout and Pin Descriptions
Table 1-1. CX28250 Pin Definitions (2 of 12)
1-8
LTxClk–
LTxClk+
LTxClkO–
LTxClkO+
LTxData–
LTxData+
LRxClk–
LRxClk+
LRxData–
LRxData+
LSigDet
Pin Label
Line Transmit Clock
Input Negative
Polarity
Line Transmit Clock
Input Positive
Polarity
Line Transmit Clock
Output Negative
Polarity
Line Transmit Clock
Output Positive
Polarity
Line Transmit Output
Negative Polarity
Line Transmit Output
Positive Polarity
Line Receive Clock
Negative
Line Receive Clock
Positive
Line Receive Input
Negative
Line Receive Input
Positive
Line Signal Detection
Signal Name
Mindspeed Technologies
M10
No.
K12
L12
P10
M8
K4
P7
P8
N8
L2
L9
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
PECL
Type
TTL
I/O
O
O
O
O
I
I
I
I
I
I
I
155.52 Mhz line transmit clock input. An external
line-rate clock may optionally be provided on this
input to drive the SONET/SDH transmit line data when
the transmit synthesizer nor loop timing mode is
enabled. This clock source is selected by bits 3 and 4
in the CLKREC register (0x01). The clock source
should be 155.52 Mhz with an accuracy of +/- 20
PPM. Tie this pin high through a 10K resistor if
unused.
Complement of the above PECL Line Transmit Clock
input. Tie this pin low through a 10 K resistor if
unused.
155.52 Mhz clock output derived from one of three
clock sources: transmit synthesizer, recovered
receive clock, or the LTxClkI+/- Inputs. The clock
source is selected by bits 3 and 4 of the CLKREC
register (0x01). It is generally used for diagnostic
purposes.
Complement of the above PECL Line Transmit Clock
output.
SONET/SDH formatted Line Transmit Data.
Complement of the above PECL Line Transmit Data
output.
155.52 Mhz line receive clock input. An external
line-rate clock may optionally be provided on this
input to clock the SONET/SDH receive line data when
the internal CDR is not being used. This clock source
can be selected by bit 5 of the CLKREC register
(0x01). The clock source should be 155.52 Mhz with
an accuracy of +/- 20 PPM. Tie this pin high through a
10K resistor if unused.
Complement of the above PECL Line Receive Clock
input. Tie this pin low through a 10K resistor if
unused.
SONET/SDH Line Receive Data.
Complement of the above PECL Line Receive Data
input.
This pin is normally connected to the Signal Valid
output of the PMD and must be asserted high when
the PMD is receiving a valid signal. Designs that do
not use a Signal Valid from the PMD must tie this
input high.
™
ATM Physical Interface (PHY) Devices
Description
28250-DSH-002-C
CX28250