cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 140

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x27—RXHDR4 (Receive Cell Header Control Register 4)
The RXHDR4 register contains the fourth byte of the Receive Cell Header. The header values direct ATM cells
to the UTOPIA port. If an incoming ATM cell header matches the value in the header register, the cell is
directed to the UTOPIA port. Receive Header Mask registers further qualify ATM cell reception. This header
consists of 32 bits divided among four registers.
0x2C—RXIDL1 (Receive Idle Cell Header Control Register 1)
The RXIDL1 register contains the first byte of the Receive Idle Cell Header. It defines ATM idle cells for the
cell receiver. Idle cells are counted and discarded from the received stream if DelIdle, bit 6 in the CVAL register
(0x08), is set to 1. This header consists of 32 bits divided among four registers.
4-42
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RxHdr4[7]
RxHdr4[6]
RxHdr4[5]
RxHdr4[4]
RxHdr4[3]
RxHdr4[2]
RxHdr4[1]
RxHdr4[0]
RxIdl1[7]
RxIdl1[6]
RxIdl1[5]
RxIdl1[4]
RxIdl1[3]
RxIdl1[2]
RxIdl1[1]
RxIdl1[0]
Name
Name
Mindspeed Technologies
These bits hold the Receive Header values for Octet 4 of the incoming cell.
These bits hold the Receive Idle cell header for Octet 1 of the incoming cell.
™
Description
Description
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250