cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 125

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
0x00—GEN (General Control Register)
The GEN register controls the receiver hold input pin, one-second latch enables, block mode error counting,
status pin selection, and device reset.
28250-DSH-002-C
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
User-defined Mode
EnCntrLat
EnStatLat
BlkMode
EnIntPin
MstRst
LgcRst
Name
—
Reserved, set to 0.
When written to a logic 1, this bit enables the MInt* pin.
status latching is enabled, the registers indicated in
with new status information after a rising edge of the OneSecIn pin. Status information
in these registers is updated continuously if one-second status latching is disabled.
one-second counter latching is enabled, the registers indicated in
is updated with new count information after a rising edge of the OneSecIn pin. Count
information in these registers is updated continuously if one-second counter latching
is disabled.
REI counters. When this mode is enabled, a received BIP (section, line, and path) or
REI (line and path) error increments the counter value by one count for each errored
frame. There are 5 counters; B1Cnt, B2Cnt, B3Cnt, LFCnt and PFCnt. When this bit is
written to 0, the actual number of BIP or REI errors received is added to the counter
value.
mode is enabled, the StatOut[7:0] pins reflect the values in the OUTSTAT control
register (0x02). When this bit is written to 0, output status for LOS, OOF, LOP, AIS-L,
RDI-L, AIS-P, RDI-P and LOCD appears on the StatOut[7:0] pins or Data Link outputs.
NOTE:
When written to a logic 1, this bit initiates a Logic Reset. When the device resets, all
internal state machines are reset, but all registers (0x00 to 0x7F) listed as “Type: W/R”
in
resets, internal state machines are held in reset, all registers (0x00 to 0x7F) assume
their default values and Bits 1-7 in this register are overwritten with their default
values.
When written to a logic 1, this bit enables 1-second status latching. When one-second
When written to a logic 1, this bit enables 1-second counter latching. When
When written to a logic 1, this bit enables the Block Error Mode operation for BIP and
When written to a logic 1, this bit enables the Status Output Pin Mode. When this
When written to a logic 1, this bit initiates a device Master Reset. When the device
Mindspeed Technologies
Table 4-1
This feature is overridden by the Data Link enables: EnTxSecDL (bit 6) in the
TXSEC register (0x0C), EnTxLinDL (bit 4) in the TXLIN register (0x0D), EnRx-
SecDL (bit 0), and EnRxLinDL (bit 1) in the RXLIN register (0x46). See
Section
are unaltered.
2.3.3.4.
Description
™
Table
4-1, footnote 2 is updated
Table
4-1, footnote 3
4.0 Registers
4.1 Registers
4-27