cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 68

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.4 ATM Cell Processor
Table 2-13. Control Bit Functions
2-32
NOTE(S):
1. The HEC Error Correction circuit is independent of the DisHECChk control bit. The CX28250 will correct single bit errors even
DisLOCD
when the DisHECChk is enabled (assuming that the EnHECCor bit is set to 1).
Non-Standard Traffic
2.4.2.2 Processing
0
0
1
1
Using the CX28250
DisHECChk
0
1
0
1
Normal operation; used for standard ATM traffic.
Cells are output to the UTOPIA FIFO only after cell delineation is found. Only cells with valid HECs
are passed (this includes cells with single bit errors that have been corrected).
Ignore HEC Errors Mode; used for IMA applications.
The Cell Delineator state machine is active and looking for valid ATM cells. It will follow the ATM
Forum’s Cell Delineation process. However, since the Cell Valid State machine is turned off, the
CX28250 will pass all cells, including those with HEC errors, to the UTOPIA FIFOs.
The CX28250 will not transfer cells during LOCD.
The cell delineation function is disabled and every 53 bytes of incoming data is treated as a ‘cell’.
However, since the CV machine is still active, only cells with valid HECs will be output. As a result,
almost all data will be dropped. Occasionally, random data will have what appears to be a valid
HEC and will be output. Mindspeed is not aware of any use for this mode.
Raw Data mode; allows the CX28250 to be used as a generic ‘serial to parallel’ convertor.
All data received will be passed across the UTOPIA bus in blocks of 53 bytes. No attempt is made
to find ATM cells.
The CX28250 contains two independent “HEC Check” state machines. The Cell
Delineator (CD) State Machine is used to find Cell Delineation and, conversely,
to declare loss of cell delineation (LOCD). The other is the Cell Valid (CV) State
Machine, which is used to validate the cells to pass to the UTOPIA FIFOs.
0x0C), that allow the CX28250 to be programmed for special applications.
Table 2-13
These state machines are controlled by two register bits, (CVAL register,
Mindspeed Technologies
shows the control bits function.
Description
™
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250