cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 150

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x3C—SUMINT (Summary Interrupt Indication Status Register)
The SUMINT register indicates data link interrupts, one-second interrupts, and additional summary interrupts.
4-52
NOTE(S):
(1)
(2)
Bit
Single event—A 0–> 1 transition on the corresponding status bit causes this interrupt to occur provided that this interrupt has
been enabled by the corresponding enable bit. Reading this interrupt register clears this interrupt.
These bits are summary indications of any interrupt events set in the indicated registers. These bits can serve as direction to
which status registers need to be read next. These bits are cleared when the interrupt bits in the indicated individual interrupt
registers are read and cleared.
7
6
5
4
3
2
1
0
Default
0
x
x
x
x
x
x
x
OneSecInt
RxCellInt
TxCellInt
APSInt
SecInt
PthInt
LinInt
Name
—
(2)
(2)
(2)
(2)
(2)
(2)
(1)
When a logic 1 is read, this bit indicates a SONET Section Interrupt. This interrupt is a
summary interrupt and signifies that an interrupt indication has occurred in the
SECINT register (0x3D).
When a logic 1 is read, this bit indicates a SONET Line Interrupt. This interrupt is a
summary interrupt and signifies that an interrupt indication has occurred in the
LININT register (0x3E).
When a logic 1 is read, this bit indicates a SONET Path Interrupt. This interrupt is a
summary interrupt and signifies that an interrupt indication has occurred in the
PTHINT register (0x3F).
When a logic 1 is read, this bit indicates a One Second Interrupt. This interrupt
signifies that a rising edge occurred on the OneSecIn pin. The interrupt is generated
for each rising edge on the OneSecIn pin and is cleared upon a read of this status
register.
Reserved, set to 0.
When a logic 1 is read, this bit indicates an APS Interrupt. This interrupt is a summary
interrupt and signifies that an interrupt indication has occurred in the APSINT register
(0x42). Set this bit to 0 on LAN parts.
When a logic 1 is read, this bit indicates a Receive Cell Interrupt. This interrupt is a
summary interrupt and signifies that an interrupt indication has occurred in the
Receive Cell Indication Register (0x41).
When a logic 1 is read, this bit indicates a Transmit Cell/UTOPIA Interrupt. This
interrupt is a summary interrupt and signifies that an interrupt indication has occurred
in the Transmit Cell Indication Register (0x40).
Mindspeed Technologies
Description
™
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250