cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 155

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
0x1E—TXHDR3 (Transmit Cell Header Control Register 3)
The TXHDR3 register contains the third byte of the Transmit Cell Header. This header consists of 32 bits
divided among four registers. Cell generation is described in detail in
0x1F—TXHDR4 (Transmit Cell Header Control Register 4)
The TXHDR4 register contains the fourth byte of the Transmit Cell Header. This header consists of 32 bits
divided among four registers. Cell generation is described in detail in
28250-DSH-002-C
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TxHdr3[7]
TxHdr3[6]
TxHdr3[5]
TxHdr3[4]
TxHdr3[3]
TxHdr3[2]
TxHdr3[1]
TxHdr3[0]
TxHdr4[7]
TxHdr4[6]
TxHdr4[5]
TxHdr4[4]
TxHdr4[3]
TxHdr4[2]
TxHdr4[1]
TxHdr4[0]
Name
Name
These bits hold the Transmit Header values for Octet 3 of the outgoing cell. Insertion of
the bits is controlled by the CGEN register (0x04).
These bits hold the Transmit Header values for Octet 4 of the outgoing cell. Insertion of
the bits is controlled by the CGEN register (0x04).
Cell Loss Priority bit
Mindspeed Technologies
VCI bits. (Bit 0 is the VCI LSB.)
VCI bits. (Bit 4 is the VCI LSB).
Payload-type bits
Description
Description
Section
Section
™
2.4.
2.4.
4.0 Registers
4.1 Registers
4-57