cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 73

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
2.5.3 UTOPIA Parity
28250-DSH-002-C
2.5.2.1 User defined
UDF2 value (receive
only)
When running in UTOPIA level 2, 16 bit mode, specify the contents of the UDF2
octet being sent from the PHY to the ATM layer by writing the desired value to
the UDF2 control register, 0x74. This can be used to “label” incoming cells with
the UTOPIA port number that received them.
The CX28250 supports even and odd parity, which is controlled by bit 2 of the
UTOP1 register (0x0A). The parity on received data is calculated for either 8 bits
or 16 bits, according to the selected bus width in bit 3 of the UTOP1 register
(0x0A). The result is output on URxPrty.
bits, according to the selected bus width. The calculated result should match the
bit present on UTxPrty. If it does not match, a parity error has occurred. This
error can be observed either in the ParErr bit (bit 7) in the TXCELL register
(0x48) or in the ParErrInt bit (bit 7) in the TXCELLINT register (0x40). Systems
that do not use parity should disable the generation of interrupts caused by parity
errors by writing bit 7 of the ENCELLT register (0x38) to 0.
This octet is ignored in UTOPIA level 1 or UTOPIA level 2, 8 bit mode.
Likewise, the parity on transmitted data is calculated for either 8 bits or 16
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2.0 Functional Description
2.5 UTOPIA Interface
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