cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 160

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x0E—TXPTH (Transmit Path Overhead Control Register)
The TXPTH register controls the transmission of various octets in the Path Overhead of the SONET frame.
0x69—TXPTHBUF (Transmit Path Trace Circular Buffer)
The TXPTHBUF buffer, the J1 byte, is used to transmit repeatedly a 64-byte, fixed-length string so that a
receiving terminal in a path can verify its continued connection to the intended transmitter.
4-62
NOTE(S):
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Bit
Bit
Transmit RDI bits 5 and 7 are reversed as compared to Receive G1 Overhead Status register (0x 19–RX G1). See 0x19—RXG1
(Receive G1 Overhead Status register) on page 4-35.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
x
x
x
x
x
x
x
x
0
0
1
0
0
0
1
1
TxPthBuf[7]
TxPthBuf[6]
TxPthBuf[5]
TxPthBuf[4]
TxPthBuf[3]
TxPthBuf[2]
TxPthBuf[1]
TxPthBuf[0]
AutoPthRDI
AutoPthREI
InsPthAIS
TxRDI[7]
TxRDI[6]
TxRDI[5]
Name
EnPthTr
Name
DisB3
Transmit Path Trace Circular Buffer bit 7.
Transmit Path Trace Circular Buffer bit 6.
Transmit Path Trace Circular Buffer bit 5.
Transmit Path Trace Circular Buffer bit 4.
Transmit Path Trace Circular Buffer bit 3.
Transmit Path Trace Circular Buffer bit 2.
Transmit Path Trace Circular Buffer bit 1.
Transmit Path Trace Circular Buffer bit 0.
When written to a logic 1, this bit enables the Path Trace Message (J1). When written
to 0, the J1 byte contains 00.
When written to a logic 1, this bit disables the BIP calculation for the Path Overhead.
When disabled, the B3 byte is set to 00. When written to 0, the BIP calculation is
enabled, and the result is placed in the B3 byte.
When written to a logic 1, this bit enables Automatic Path REI. When enabled, path
REI codes are automatically inserted upon reception of path BIP errors. When written
to 0, Automatic Path REI is not enabled.
When written to a logic 1, this bit inserts Path AIS. When written to 0, Path AIS is not
inserted.
This value is mapped to Transmit RDI bit 7 in the G1 path overhead octet.
This value is mapped to Transmit RDI bit 6 in the G1 path overhead octet.
This value is mapped to Transmit RDI bit 5 in the G1 path overhead octet.
When written to a logic 1, this bit enables Automatic Path RDI. When enabled, path
RDI is automatically generated (for 10 frames for the CX28250-23 device or 20
frames for the CX28250-26 device) upon reception of LOS, LOF, LOP, AIS-L, AIS-P,
UNEQ-P, or PLM-P. When none of the above alarms are present path RDI (G1, bits
5-7) is inserted from bits [3:1] of this register.
register.
Mindspeed Technologies
When written to 0, path RDI (G1, bits 5-7) is inserted from bits [1:3] of this
Description
Description
™
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250
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