cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 159

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
0x0D—TXLIN (Transmit Line Overhead Control Register)
The TXLIN register controls the transmission of various octets in the Line Overhead of the SONET frame.
28250-DSH-002-C
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
1
1
AutoLnRDI
EnTxLinDL
AutoLnREI
STMMode
InsLnRDI
InsLnAIS
DisPntr
Name
DisB2
When written to a logic 1, this bit enables the SDH STM-1 Mode pointer. When
enabled, the H1/H2 bytes are 6A/0A. When written to 0, the H1/H2 bytes are set to
62/0A for SONET applications. For OC-3c, bit 6 (DisPntr) overrides this function.
When this bit is written to a logic 1, the H1/H2 Overhead bytes are forced to 33, When
written to 0, the H1/H2 value is determined by bit 7.
When written to a logic 1, this bit disables the BIP calculations for the Line Overhead.
When disabled, the B2 bytes are set to 00. When written to 0, the BIP calculations are
enabled, and the results are placed in the B2 bytes.
When written to a logic 1, this bit enables the Transmit D4-D12 bytes of the Data Link.
When written to 0, these bytes are forced to all 00.
When written to a logic 1, this bit inserts Line AIS. All bits except the section overhead
octets are written to a logic 1 prior to scrambling. When written to 0, Line AIS is not
inserted.
When written to a logic 1, this bit inserts Line RDI. K2 bits 6, 7, and 8 are set to 110.
When written to 0, K2 bits 6, 7, and 8 are set to the values of the bits 6, 7, and 8 in the
TxK2 register.
When written to a logic 1, this bit enables Automatic Line RDI. When enabled, line RDI
is automatically generated (for 5 frames for the CX28250-23 device or 20 frames for
the CX28250-26 device) upon reception of LOS, LOF, or AIS-L. When written to 0,
Automatic Line RDI is disabled.
When written to a logic 1, this bit enables Automatic Line REI. When written to 1, line
REI codes are automatically inserted upon reception of line BIP errors. When written
to 0, Automatic Line REI is disabled.
Mindspeed Technologies
Description
™
4.0 Registers
4.1 Registers
4-61