cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 85

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
2.7.2 UTOPIA Loopback
Figure 2-16. UTOPIA Loopback Diagram
28250-DSH-002-C
PECL Logic
LRxData+/-
ATM WIRE
LTxClkO+/-
LTxData+/-
Interface
LTxClkI+/-
LRxClk+/-
SigDet
Level
(19.44 MHz)
PLLCLK
TCK
Line Interface
TRST*
and Clock
Recovery
Controller
Transmit
Interface
Receive
JTAG
Line
8kHzIn
TMS
Loopback
Control
TDI
TDO
TxDL
UTOPIA loopback is enabled or disabled by bit 0 of the CLKREC register (0x01).
When UTOPIA loopback is enabled, all received cells in the UTOPIA FIFO are
passed to the transmit FIFO for transmission on the Transmit Line Interface. The
receive UTOPIA bus is placed in a high-impedance state.
Tx Overhead
Rx Overhead
SONET Line Framer
Extract
Insert
Transmit Framer
Receive Framer
STS-3c/STM-1
STS-3c/STM-1
Mindspeed Technologies
StatOut[0:7]
Status
InsPthAIS
ATM Cell Framer
InsLnAIS
Performance Monitoring
Receive Cell
MRdy
Alignment
Interrupt Control
Cell Counters
OneSecIn
Generation
Clock and
OneSecOut
Tx Cell
Control
MInt*
™
RxFrameRef
Rx VPI/VCI
Screening
Validation
MAddr[6:0]
Rx Cell
TxFrameRef
Microprocessor
MData[7:0]
Interface
2.0 Functional Description
PFOut
Interface
Interface
Transmit
UTOPIA
Receive
UTOPIA
Level 2
Level 2
4-cell
4-cell
FIFO
Control Lines
FIFO
Host
Host
2.7 Loopback Modes
LFOut
Interface
UTOPIA
Level 2
UTxClk
UTxClAv
UTxEnb*
UTxSOC
UTxData[15:0]
TxPrty
UTxAddr[4:0]
URxClk
URxClAv
URxEnb*
URxSOC
URxData[15:0]
URxPrty
URxAddr[4:0]
500035_019
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