cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 78

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.6 Microprocessor Interface
2.6.4 One-second Latching
2-42
Mindspeed’s implementation of one-second latching ensures the integrity of the
statistics being gathered by the network management software. Internal statistics
counters can be latched at one-second intervals, which are synchronized to the
OneSecIn pin. Therefore, the data read from the statistic counters represents the
same “one second” of real-time data, independent of network management
software timing.
counter values. When the EnStatLat bit (5) in the GEN register (0x00) is written
to a logic 1, a read from any of the status registers returns the state of the device at
the time of the previous OneSecIn pin assertion. When the EnCntrLat bit (4) in
the GEN register (0x00) is written to a logic 1, a read from any of the counters
returns the state of the device at the time of the previous OneSecIn pin assertion.
Thus the counters are updated once per second.
be achieved by connecting the OneSecIn pin to the OneSecOut pin. The
OneSecOut signal is derived from the 8kHzIn pin. This signal is asserted for one
8kHzIn clock period, every 8,000 8kHzIn periods. If 8kHzIn is being driven by an
8 kHz clock, the OneSecOut signal is asserted every second.
NOTE:
The CX28250 implements one-second latching for both status signals and
The OneSecIn pin is intended to be asserted at one-second intervals. This can
When latching is disabled and a counter is wider than one byte, the LSB
should be read first which retains the values of the other bytes for a
subsequent read.
Mindspeed Technologies
™
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250