cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 18

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

1.0 Product Description
1.1 CX28250 Features
1-2
1.1 CX28250 Features
The CX28250, operating at up to 155 Mbps (duplex), provides a single-access
ATM service termination for User-to-Network Interfacing (UNI) and
Network-to-Network Interfacing (NNI) in conformance with the ATM Forum UNI
Specification 94/0317, ITU Recommendation I.432, and other industry standards.
This PHY device consists of several functional blocks: the SONET Framer, the
ATM Cell Formatter, the UTOPIA Level 2 interface, and the microprocessor
interface. Together these blocks and the clock recovery block provide efficient
conversion of SONET frames to ATM cells and vice versa.
on 3.3 V , and is packaged in a 156-pin Ball Grid Array (BGA). This low-power
device processes STS-3c/STM-1 data streams at 155 Mbps (duplex) and provides
a Pseudo-Emitter Coupled Logic (PECL) interface for serial connection to a
Physical Media Dependent (PMD) device. It has a synchronous 16-bit wide,
four-cell deep FIFO buffer and an 8-bit microprocessor bus interface, which is
used for configuration, status, and control of the device. Furthermore, the
CX28250 output control signals can drive Light Emitting Diodes (LEDs) for
monitoring data and alarm activity.
H2) to locate and retrieve the SONET payload envelope. It also processes section,
line, and path overhead. ATM cells are extracted from the payload envelope
according to the ATM cell delineation standards. The CX28250 optionally
performs payload descrambling, Header Error Checking (HEC) error detection
and correction, and idle cell filtering. Error counts are kept at all levels for
performance monitoring.
bytes (A1, A2). The device also performs HEC generation, idle cell insertion, and
ATM cell payload scrambling. The CX28250 synthesizes the 155.52 MHz
transmit clock from a 19.44 MHz, 8 kHz frequency reference, or can use the
clock from the internal clock recovery circuit.
Defect Indications (RDIs). It also inserts path and line REI codes to allow
performance monitoring at the far end. Additionally, all-0s data can be inserted
for diagnostic purposes.
alarm condition has occurred. These pins are software configurable.
The CX28250 is implemented in 0.35 micron CMOS technology, which runs
The CX28250 descrambles received data, then uses the payload pointer (H1,
The CX28250 generates a transmit payload pointer (H1, H2) and framing
When necessary, the CX28250 inserts line and path alarm signals and Remote
The two Far End status output pins indicate whether a Path Fail or Line Fail
Mindspeed Technologies
™
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250