cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 52

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.3 SONET/SDH Framer and Overhead Processor
2-16
In the -23 Version Only
Z0 Receive Value
Z2 Receive Value
2.3.2.6 Z0
2.3.2.5 J0
Z0 Transmit
The Section Trace byte, J0, is connected to a circular 64-byte buffer, carrying the
Section Trace message, which allows section elements to track a continuous
connection. This buffer overwrites when full. This message is user-programmable
but generally is an 8-bit ASCII CLLI™ code padded with ASCII NULL
characters and terminated with CR and LF characters making up 64 bytes total. If
Section Trace is enabled, the user is required to enter a message or the current
contents of the transmit buffer will be transmitted. The J0 transmit buffer is
located in register TXSECBUF (0x68). J0 can be disabled via register TXSEC
(0x0C), bit 5. If J0 is disabled the transmitted J0 byte will be set to 0x01. The J0
receive buffer is accessed via RXSECBUF (0x6A). If the incoming message
differs from the previous message stored in the receive buffer an interrupt appears
in register SECINT (0x3D) bit 1. The J0 transmit and receive circular buffers
operate the same as the J1 byte circular buffers; See
regardless of any incoming receive errors.
NOTE:
The CX28250-23 version does not have a three-frame integrator. Therefore, any
change in the incoming messages generates an interrupt.
Full access to both Z0 transmit and receive octects is provided.
The Section Growth bytes, Z0
respectively. These values can be overwritten by changing the contents of the
TXZ0
The incoming Z0 octets from the SONET overhead are latched into the RXZ0
0x1A, and RXZ0
value changes and the interrupt is enabled, a single event interrupt is generated in
bit 1 of the LinInt Register, 0x3E. Note that this interrupt is shared with the Z2
octet.
The incoming Z2 octet from the SONET overhead is latched into the RXZ
registers after a 3 frame integration period. If the value changes and the interrupt
is enabled, a single event interrupt is generated in bit 1 of the LinInt Register,
0x3E. Note that this interrupt is shared with the Z0
• A receive trace message must be received three times before a new value is
• Receive J0 trace buffer contents are updated as described above at all times
• Transmit buffer contents are transmitted at all times (when enabled)
1
latched into the receive trace buffer. At the completion of the three frame
integration period an interrupt will be generated to signal that the trace
message contents have changed. Intermittent changes to these bytes over
consecutive frames will not trigger erroneous interrupts. This reduces the
impact on software performance and effort.
except during LOS or OOF conditions. During these conditions, buffer
contents will remain unchanged from previous values.
It takes 192 SONET frames to transmit 3 complete trace buffers.
and TXZ0
Mindspeed Technologies
2
2
, 0x1B, registers after a 3 frame integration period. If either
registers.
1
and Z0
2
, are set to defaults of 02 and 03,
™
ATM Physical Interface (PHY) Devices
1
Figure
and Z0
2-10.
2
octets.
28250-DSH-002-C
CX28250
2
, 0x17,
1
,