cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 120

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x38—ENCELLT (Transmit Cell Interrupt Mask Control Register)
The ENCELLT register controls which of the interrupts listed in the TxCellInt register (0x40) appear on the
MInt* pin, provided that EnTxCellInt (bit 0) in the ENSUMINT register (0x34) is enabled, and EnIntPin (bit 6)
in the GEN register (0x00) is enabled.
0x6E—ENLFOUT (Enable Line Fail Output)
This register controls which events will cause the LFOut pin to be asserted:
4-22
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
EnCellSent
EnSOCErr
EnRxOvfl
EnParErr
EnTxOvfl
Name
Name
LOP-P
AIS-L
AIS-P
LOCD
LOS
OOF
LOL
LOF
—
—
—
When written to a logic 1, this bit enables the Parity Error Interrupt. When enabled, the
interrupt appears on the MInt* pin for the ParErr interrupt indication bit.
When written to a logic 1, this bit enables the Start of Cell Alignment Error Interrupt.
When enabled, the interrupt appears on the MInt* pin for the SOCErr interrupt
indication bit.
When written to a logic 1, this bit enables the Transmit FIFO Overflow Interrupt. When
enabled, the interrupt appears on the MInt* pin for the TxOvfl interrupt indication bit.
When written to a logic 1, this bit enables the Receive FIFO Overflow Interrupt. When
enabled, the interrupt appears on the MInt* pin for the RxOvfl interrupt indication bit.
When written to a logic 1, this bit enables the Cell Sent Interrupt. When enabled, the
interrupt appears on the MInt* pin for the CellSent interrupt indication bit.
Reserved, set to 0.
Reserved, set to 0.
Reserved, set to 0.
When enabled, assertion of LOS status bit will cause the LFOut pin to be asserted.
When enabled, assertion of LOL status bit will cause the LFOut pin to be asserted.
When enabled, assertion of OOF status bit will cause the LFOut pin to be asserted.
When enabled, assertion of LOF status bit will cause the LFOut pin to be asserted.
When enabled, assertion of AIS-L status bit will cause the LFOut pin to be asserted.
When enabled, assertion of AIS-P status bit will cause the LFOut pin to be asserted.
When enabled, assertion of LOP-P status bit will cause the LFOut pin to be asserted.
When enabled, assertion of LOCD status bit will cause the LFOut pin to be asserted.
Mindspeed Technologies
Description
Description
™
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250