cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 142

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

4.0 Registers
4.1 Registers
0x2F—RXIDL4 (Receive Idle Cell Header Control Register 4)
The RXIDL4 register contains the fourth byte of the Receive Idle Cell Header. It defines ATM idle cells for the
cell receiver. Idle cells are counted and discarded from the received stream if DelIdle, bit 6 in the CVAL register
(0x08), is set to 1. This header consists of 32 bits divided among four registers.
0x14—RXK1 (Receive K1 Overhead Status Register)
The RXK1 register provides K1 overhead status. The K1 and K2 bytes are allocated for Automatic Protection
Switching (APS) signaling between Line level entities. These bytes are defined only for the first STS-1 of the
STS-3c signal.
4-44
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
1
x
x
x
x
x
x
x
x
RxK1[1]
RxK1[2]
RxK1[3]
RxK1[4]
RxK1[5]
RxK1[6]
RxK1[7]
RxK1[8]
RxIdl4[7]
RxIdl4[6]
RxIdl4[5]
RxIdl4[4]
RxIdl4[3]
RxIdl4[2]
RxIdl4[1]
RxIdl4[0]
Name
Name
Receive value for K1 Overhead Octet—bit 1 (MSB)
Receive value for K1 Overhead Octet—bit 2
Receive value for K1 Overhead Octet—bit 3
Receive value for K1 Overhead Octet—bit 4
Receive value for K1 Overhead Octet—bit 5
Receive value for K1 Overhead Octet—bit 6
Receive value for K1 Overhead Octet—bit 7
Receive value for K1 Overhead Octet—bit 8 (LSB)
Mindspeed Technologies
These bits hold the Receive Idle cell header for Octet 4 of the incoming cell.
Description
™
Description
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
CX28250