cx28250 Mindspeed Technologies, cx28250 Datasheet - Page 61

• Manufacturer Part Number: cx28250
• Description: Cx28250 Atm Physical Interface Phy Devices
• Manufacturer: Mindspeed Technologies

CX28250
ATM Physical Interface (PHY) Devices
28250-DSH-002-C
In the -26 Version Only
2.3.4.2 B3
2.3.4.3 C2
NOTE:
The Path BIP-8 byte, B3, is allocated for path error monitoring. The path B3 byte
is calculated over all bits of the previous STS SPE frame before scrambling, using
bit-interleaved parity 8 code with even parity. As many as 64 k errors per second
can be detected. B3 can be disabled by writing bit 6 in the TXPTH (0x0E) register
to 1.
programmable BER thresholds to allow the generation of interrupts. This is
identical to the APS (B2) error reporting except the thresholds are programmable
from 10
version.
The Path Signal label byte, C2, identifies the type of payload being received. The
default code transmitted by the CX28250 is 13 hex for ATM mapping. However,
it can be changed to any other value in the TXC2 register (0x13). The receiver
expects 01, 13, FC, or FF hex to be received as valid code words. The SONET
block monitors the incoming C2 and generates one of two possible interrupts if 5
consecutive invalid values are received. If the received value is 00 hex, an
Unequipped Path (Uneq-P) interrupt is generated in bit 2 in the PTHINT register
(0x3F). If any other invalid value is received, a Payload Label Mismatch in Path
(PLM-P) interrupt is generated in bit 3 in the PTHINT register.
• A receive trace message must be received three times before a new value is
• Receive J1 trace buffer contents are updated as described above at all times
• Transmit buffer contents are transmitted at all times (when enabled)
In addition to counting B3 errors, the CX28250-26 version of the device has
latched into the receive trace buffer. At the completion of the three frame
integration period an interrupt will be generated to signal that the trace
message contents have changed. Intermittent changes to these bytes over
consecutive frames will not trigger erroneous interrupts. This reduces the
impact on software performance and effort.
except during LOS, LOF, AIS-L, AIS-P, or LOP-P conditions. During
these conditions, the buffer contents will remain unchanged from previous
values.
regardless of any incoming receive errors.
It takes 192 SONET frames to transmit 3 complete trace buffers.
–4
Mindspeed Technologies
to 10
–9
(refer to
Table
2-7). This only applies to the CX28250-26
2.3 SONET/SDH Framer and Overhead Processor
™
2.0 Functional Description
2-25