DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 101

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

4.1
4.1.1
As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is
prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in
order of priority. Trap instruction exceptions are accepted at all times, in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control
mode set by the INTM0 and INTM1 bits of SYSCR.
Table 4-1
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on
3. Trap instruction exception handling requests are accepted at all times in program execution state.
4. Manual reset is only supported in the H8S/2357 ZTAT.
Overview
Exception Handling Types and Priority
of an RTE instruction.
completion of reset exception handling.
Priority
High
Low
Exception Types and Priority
Exception Type
Reset
Trace*
Interrupt
Trap instruction (TRAPA)*
1
Section 4 Exception Handling
3
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU enters
the power-on reset state when the NMI pin is high, or the
manual reset*
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued*
Started by execution of a trap instruction (TRAPA)
4
state when the NMI pin is low.
Rev.6.00 Oct.28.2004 page 71 of 1016
REJ09B0138-0600H
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