DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 524

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

[3] The SCI checks the TDRE flag at the timing for sending the stop bit.
Figure 14-6 shows an example of the operation for transmission in asynchronous mode.
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REJ09B0138-0600H
[b] Transmit data:
[c] Parity bit or multiprocessor bit:
[d] Stop bit(s):
[e] Mark state:
If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial
transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark state” is entered
in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated.
8-bit or 7-bit data is output in LSB-first order.
One parity bit (even or odd parity), or one multiprocessor bit is output.
A format in which neither a parity bit nor a multiprocessor bit is output can also be selected.
One or two 1-bits (stop bits) are output.
1 is output continuously until the start bit that starts the next transmission is sent.
TDRE
TEND
TXI interrupt
request generated
1
Figure 14-6 Example of Operation in Transmission in Asynchronous Mode
Start
bit
0
Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt service routine
D0
D1
(Example with 8-Bit Data, Parity, One Stop Bit)
1 frame
Data
D7
Parity
bit
0/1
TXI interrupt
request generated
Stop
bit
1
Start
bit
0
D0
D1
Data
D7
Parity
bit
0/1
TEI interrupt
request generated
Stop
bit
1
Idle state
(mark state)
1