DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 441

IC H8S MCU FLASH 256K 120TQFP

DF2398TE20

Manufacturer Part Number
DF2398TE20
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2398TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2398TE20
HD64F2398TE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
11.1
The H8S/2357 Group has a on-chip programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit
timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 to group 0) that can
operate both simultaneously and independently.
11.1.1
PPG features are listed below.
16-bit output data
Four output groups
Selectable output trigger signals
Non-overlap mode
Can operate together with the data transfer controller (DTC) and DMA controller (DMAC)
Settable inverted output
Module stop mode can be set
Maximum 16-bit data can be output, and output can be enabled on a bit-by-bit basis
Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs
Output trigger signals can be selected for each group from the compare match signals of four TPU channels
A non-overlap margin can be provided between pulse outputs
The compare match signals selected as output trigger signals can activate the DTC or DMAC for sequential output
Inverted data can be output for each group
As the initial setting, PPG operation is halted. Register access is enabled by exiting module stop mode
of data without CPU intervention
Overview
Features
Section 11 Programmable Pulse Generator (PPG)
Rev.6.00 Oct.28.2004 page 411 of 1016
REJ09B0138-0600H

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