DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 125
DF2398TE20
Manufacturer Part Number
DF2398TE20
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2398TE20
HD64F2398TE20
HD64F2398TE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 125 of 1049
- Download datasheet (5Mb)
5.4.3
Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the
interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR.
Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case.
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the
[2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the
[3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt
[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has
[5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows
[6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt.
[7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the
interrupt controller.
interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of
interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority
according to the priority system shown in table 5-4 is selected.
request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with
a priority higher than the interrupt mask level is accepted.
been completed.
the address of the first instruction to be executed after returning from the interrupt handling routine.
If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
address indicated by the contents of that vector address.
Interrupt Control Mode 2
Rev.6.00 Oct.28.2004 page 95 of 1016
REJ09B0138-0600H
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