DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 458

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output):
Figure 11-7 shows an example in which pulse output is used for four-phase complementary non-overlapping pulse output.
[1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers.
[2] Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select
[3] The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0.
[4] Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95...
Rev.6.00 Oct.28.2004 page 428 of 1016
REJ09B0138-0600H
Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare
match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt.
compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV
bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH.
When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value
set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH.
at successive TGIA interrupts. If the DTC or DMAC is set for activation by this interrupt, pulse output can be
obtained without imposing a load on the CPU.
H'0000
NDRH
PODRH
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 11-7 Non-Overlapping Pulse Output Example (Four-Phase Complementary)
TGRB
TGRA
TCNT value
95
TCNT
00
95
65
05
Non-overlap margin
65
59
41
59
56
50
56
95
14
95
65
05
65
Time