DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 246

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

Activation by External Request: If an external request (DREQ pin) is specified as an activation source, the relevant port
should be set to input mode in advance.
Level sensing or edge sensing can be used for external requests.
External request operation in normal mode (short address mode or full address mode) is described below.
When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low transition is detected on the
DREQ pin. The next transfer may not be performed if the next edge is input before transfer is completed.
When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is held high. While the
DREQ pin is held low, transfers continue in succession, with the bus being released each time a byte or word is
transferred. If the DREQ pin goes high in the middle of a transfer, the transfer is interrupted and the DMAC stands by for
a transfer request.
Activation by Auto-Request: Auto-request activation is performed by register setting only, and transfer continues to the
end.
With auto-request activation, cycle steal mode or burst mode can be selected.
In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and
CPU cycles usually alternate.
In burst mode, the DMAC keeps possession of the bus until the end of the transfer, and transfer is performed continuously.
Single Address Mode: The DMAC can operate in dual address mode in which read cycles and write cycles are separate
cycles, or single address mode in which read and write cycles are executed in parallel.
In dual address mode, transfer is performed with the source address and destination address specified separately.
In single address mode, on the other hand, transfer is performed between external space in which either the transfer source
or the transfer destination is specified by an address, and an external device for which selection is performed by means of
the DACK strobe, without regard to the address. Figure 7-17 shows the data bus in single address mode.
Rev.6.00 Oct.28.2004 page 216 of 1016
REJ09B0138-0600H
Figure 7-17 Data Bus in Single Address Mode
(high impedance)
H8S/2357
Group
HWR, LWR
D
A
15
23
DACK
to D
to A
RD
0
0
Address bus
(Read)
(Write)
External
External
memory
device