DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 493

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

13.5
13.5.1
If a timer counter clock pulse is generated during the T
counter is not incremented. Figure 13-8 shows this operation.
13.5.2
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation.
Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0.
13.5.3
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could
occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the
mode.
13.5.4
If the WDTOVF output signal* is input to the RES pin of the H8S/2357 Group, the H8S/2357 Group will not be
initialized correctly. Make sure that the WDTOVF signal* is not input logically to the RES pin. To reset the entire system
by means of the WDTOVF signal*, use the circuit shown in figure 13-9.
Note: * The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392 or
H8S/2390.
Usage Notes
Contention between Timer Counter (TCNT) Write and Increment
Changing Value of CKS2 to CKS0
Switching between Watchdog Timer Mode and Interval Timer Mode
System Reset by WDTOVF Signal
ø
Address
Internal write signal
TCNT input clock
TCNT
Figure 13-8 Contention between TCNT Write and Increment
2
TCNT write cycle
state of a TCNT write cycle, the write takes priority and the timer
T
1
N
T
2
Counter write data
Rev.6.00 Oct.28.2004 page 463 of 1016
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REJ09B0138-0600H