DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 624

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

19.9
In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU.
There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode.
Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in
FLMCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory
programming/erasing (the programming control program) should be located and executed in on-chip RAM or external
memory.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in FLMCR1, and the ESU
19.9.1
Follow the procedure shown in the program/program-verify flowchart in figure 19-19 to write data or programs to flash
memory. Performing program operations according to this flowchart will enable data or programs to be written to flash
memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be
carried out 32 bytes at a time.
The wait times (x, y, z, , ß,
FLMCR2) and the maximum number of programming operations (N) are shown in table 22.42 in section 22.7.6, Flash
Memory Characteristics.
Following the elapse of (x) s or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 32-byte
program data is stored in the program data area and reprogram data area, and the 32-byte data in the reprogram data area
written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00, H'20, H'40,
H'60, H'80, H'A0, H'C0, or H'E0. Thirty-two consecutive byte data transfers are performed. The program address and
program data are latched in the flash memory. A 32-byte data transfer must be performed even if writing fewer than 32
bytes; in this case, H'FF data must be written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than
(y + z +
setting the PSU bit in FLMCR2, and after the elapse of (y) s or more, the operating mode is switched to program mode
by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a
program setting so that the time for one programming operation is within the range of (z) s.
19.9.2
In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the
flash memory.
After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared to 0, then
the PSU bit in FLMCR2 is cleared to 0 at least ( ) s later). Next, the watchdog timer is cleared after the elapse of ( ) s
or more, and the operating mode is switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in
program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should
be executed after the elapse of ( ) s or more. When the flash memory is read in this state (verify data is read in 16-bit
units), the data at the latched address is read. Wait at least ( ) s after the dummy write before performing this read
operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure
Rev.6.00 Oct.28.2004 page 594 of 1016
REJ09B0138-0600H
2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0).
3. Perform programming in the erased state. Do not perform additional programming on previously programmed
Programming/Erasing Flash Memory
Program Mode
Program-Verify Mode
+ ß) s as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by
and PSU bits in FLMCR2, is executed by a program in flash memory.
addresses.
after bits are set or cleared in flash memory control registers 1 and 2 (FLMCR1,