DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 380

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The
TPU has six TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset, and in
hardware standby mode.
TMDR register settings should be made only when TCNT operation is stopped.
Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1.
Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to
be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not
generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified.
Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to
be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not
generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified.
Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
Rev.6.00 Oct.28.2004 page 350 of 1016
REJ09B0138-0600H
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.
Bit 5
BFB
0
1
Bit 4
BFA
0
1
Bit 3
MD3*
0
1
1
Bit 2
MD2*
0
1
Description
TGRB operates normally
TGRB and TGRD used together for buffer operation
Description
TGRA operates normally
TGRA and TGRC used together for buffer operation
2
Bit 1
MD1
0
1
0
1
Bit 0
MD0
0
1
0
1
0
1
0
1
Description
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
—
(Initial value)
(Initial value)
(Initial value)
: Don’t care