DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 171

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

6.5.7
When DRAM is accessed, RAS precharging time must be secured. With the H8S/2357 Series, one T
inserted when DRAM space is accessed. This can be changed to two T
appropriate number of T
Figure 6-16 shows the timing when two T
When the TPC bit is set to 1, two T
6.5.8
There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using
the WAIT pin.
Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from
0 to 3 wait states can be inserted automatically between the T
WCRL.
Pin Wait Insertion: When the WAITE bit in BCRH is set to 1, wait input by means of the WAIT pin is enabled
regardless of the setting of the AST bit in ASTCR. When DRAM space is accessed in this state, a program wait is first
inserted. If the WAIT pin is low at the falling edge of ø in the last T
pin is held low, T
Precharge State Control
Wait Control
Note: n = 2 to 5
Read
Write
w
states are inserted until it goes high.
HWR,
HWR,
p
CSn, (RAS)
CAS, LCAS
cycles according to the DRAM connected and the operating frequency of the H8S/2357 Group.
D
D
A
15
23
15
(WE)
(WE)
to D
to D
to A
ø
0
0
0
p
Figure 6-16 Timing with Two Precharge States
states are also used for refresh cycles.
p
states are inserted.
T
p1
T
p2
c1
state and T
c1
or T
Row
p
T
states by setting the TPC bit in MCR to 1. Set the
r
w
c2
state, another T
state, according to the settings of WCRH and
Rev.6.00 Oct.28.2004 page 141 of 1016
T
Column
c1
w
state is inserted. If the WAIT
T
c2
p
state is always
REJ09B0138-0600H