DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 181

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

6.7.2
Basic Timing
The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the
AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected
for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is
designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR.
When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to
1, burst access of up to 8 words is performed.
The basic access timing for burst ROM space is shown in figures 6-30 (a) and (b). The timing shown in figure 6-30 (a) is
for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 6-30 (b) is for the case where both these
bits are cleared to 0.
Full access
Burst access
T
T
T
T
T
T
T
1
2
3
1
2
1
2
ø
Only lower address changed
Address bus
CS0
AS
RD
Data bus
Read data
Read data
Read data
Figure 6-30 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
Rev.6.00 Oct.28.2004 page 151 of 1016
REJ09B0138-0600H