DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 19

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

7.4
7.5
7.6
7.7
Section 8 Data Transfer Controller ...................................................................................................241
8.1
8.2
8.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
Register Descriptions (3) ..........................................................................................................................................190
7.4.1
7.4.2
7.4.3
Operation ..................................................................................................................................................................194
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 DMAC Bus Cycles (Dual Address Mode) ..................................................................................................218
7.5.11 DMAC Bus Cycles (Single Address Mode) ............................................................................................... 226
7.5.12 Write Data Buffer Function......................................................................................................................... 230
7.5.13 DMAC Multi-Channel Operation ............................................................................................................... 231
7.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC ............................... 232
7.5.15 NMI Interrupts and DMAC......................................................................................................................... 233
7.5.16 Forced Termination of DMAC Operation................................................................................................... 234
7.5.17 Clearing Full Address Mode ....................................................................................................................... 235
Interrupts................................................................................................................................................................... 236
Usage Notes ..............................................................................................................................................................237
Overview................................................................................................................................................................... 241
8.1.1
8.1.2
8.1.3
Register Descriptions................................................................................................................................................244
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
Operation ..................................................................................................................................................................249
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Memory Address Register (MAR) ..............................................................................................................181
I/O Address Register (IOAR)......................................................................................................................181
Execute Transfer Count Register (ETCR)................................................................................................... 181
DMA Control Register (DMACR)..............................................................................................................183
DMA Band Control Register (DMABCR)..................................................................................................186
DMA Write Enable Register (DMAWER) ................................................................................................. 190
DMA Terminal Control Register (DMATCR)............................................................................................192
Module Stop Control Register (MSTPCR) ................................................................................................. 193
Transfer Modes ........................................................................................................................................... 194
Sequential Mode..........................................................................................................................................196
Idle Mode..................................................................................................................................................... 199
Repeat Mode ............................................................................................................................................... 201
Single Address Mode ..................................................................................................................................204
Normal Mode............................................................................................................................................... 207
Block Transfer Mode................................................................................................................................... 210
DMAC Activation Sources ......................................................................................................................... 215
Basic DMAC Bus Cycles ............................................................................................................................217
Features ....................................................................................................................................................... 241
Block Diagram............................................................................................................................................. 242
Register Configuration ................................................................................................................................243
DTC Mode Register A (MRA)....................................................................................................................244
DTC Mode Register B (MRB) ....................................................................................................................245
DTC Source Address Register (SAR)......................................................................................................... 246
DTC Destination Address Register (DAR) ................................................................................................. 246
DTC Transfer Count Register A (CRA) ..................................................................................................... 246
DTC Transfer Count Register B (CRB) ......................................................................................................246
DTC Enable Registers (DTCER) ................................................................................................................247
DTC Vector Register (DTVECR) ............................................................................................................... 247
Module Stop Control Register (MSTPCR) ................................................................................................. 248
Overview ..................................................................................................................................................... 249
Activation Sources....................................................................................................................................... 251
DTC Vector Table ....................................................................................................................................... 252
Location of Register Information in Address Space ................................................................................... 255
Normal Mode............................................................................................................................................... 256
Repeat Mode ............................................................................................................................................... 257
Rev.6.00 Oct.28.2004 page xiii of xxiv
REJ09B0138-0600H