DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 348

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

9.11.2
Table 9-19 shows the port D register configuration.
Table 9-19 Port D Registers
Note: * Lower 16 bits of the address.
Port D Data Direction Register (PDDDR) (On-Chip ROM Version Only)
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR
cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port D Data Register (PDDR) (On-Chip ROM Version Only)
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD
PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Rev.6.00 Oct.28.2004 page 318 of 1016
REJ09B0138-0600H
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Mode 7
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin
an input port.
Modes 4 to 6
The input/output direction specification by PDDDR is ignored, and port D is automatically designated for data I/O.
Register Configuration (On-Chip ROM Version Only)
Name
Port D data direction register
Port D data register
Port D register
Port D MOS pull-up control register
:
:
:
:
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
PD7DR
R/W
W
7
0
7
0
PD6DR
R/W
W
6
0
6
0
PD5DR
R/W
W
5
0
5
0
PD4DR
R/W
W
Abbreviation
PDDDR
PDDR
PORTD
PDPCR
4
0
4
0
PD3DR
R/W
W
3
0
3
0
PD2DR
R/W
W
R/W
R
R/W
R/W
W
2
0
2
0
Initial Value
H'00
H'00
Undefined
H'00
PD1DR
R/W
W
1
0
1
0
7
PD0DR
to PD
R/W
W
0
0
0
0
0
Address *
H'FEBC
H'FF6C
H'FF5C
H'FF73
).