DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 117

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

5.3
Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (52 sources).
5.3.1
There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be used to restore the
H8S/2357 Group from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the status of the
CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge
or a falling edge on the NMI pin.
The vector number for NMI interrupt exception handling is 7.
IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts
IRQ7 to IRQ0 have the following features:
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5-2.
Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both
edges, at pins IRQ7 to IRQ0.
Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
The interrupt priority level can be set with IPR.
The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software.
Interrupt Sources
External Interrupts
Bit n
IRQnF
0
1
Description
[Clearing conditions]
[Setting conditions]
Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag
When interrupt exception handling is executed when low-level detection is set
(IRQnSCB = IRQnSCA = 0) and IRQn input is high
When IRQn interrupt exception handling is executed when falling, rising, or both-edge
detection is set (IRQnSCB = 1 or IRQnSCA = 1)
When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0
When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =
0)
When a falling edge occurs in IRQn input when falling edge detection is set
(IRQnSCB = 0, IRQnSCA = 1)
When a rising edge occurs in IRQn input when rising edge detection is set
(IRQnSCB = 1, IRQnSCA = 0)
When a falling or rising edge occurs in IRQn input when both-edge detection is set
(IRQnSCB = IRQnSCA = 1)
Rev.6.00 Oct.28.2004 page 87 of 1016
(Initial value)
REJ09B0138-0600H
(n = 7 to 0)