DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 153

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

6.3.3
The H8S/2357 Group memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM,
and so on; a DRAM interface that allows direct connection of DRAM; and a burst ROM interface that allows direct
connection of burst ROM. The interface can be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface
is designated functions as DRAM space, and an area for which the burst ROM interface is designated functions as burst
ROM space.
6.3.4
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the
operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface
(section 6.4, Basic Bus Interface, section 6.5, DRAM Interface, and section 6.7, Burst ROM Interface) should be referred
to for further details.
Area 0: Area 0 includes on-chip ROM*, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-
enabled expansion mode, the space excluding on-chip ROM* is external space.
When area 0 external space is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
Note: * Applies to the on-chip ROM version only.
Areas 1 and 6: In external expansion mode, all of areas 1 and 6 is external space.
When area 1 and 6 external space is accessed, the CS1 and CS6 pin signals respectively can be output.
Only the basic bus interface can be used for areas 1 and 6.
Areas 2 to 5: In external expansion mode, all of areas 2 to 5 is external space.
When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output.
Basic bus interface or DRAM interface can be selected for areas 2 to 5. With the DRAM interface, signals CS2 to CS5 are
used as RAS signals.
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the
on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system
control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the
corresponding space becomes external space .
When area 7 external space is accessed, the CS7 signal can be output.
Only the basic bus interface can be used for the area 7 memory interface.
Memory Interfaces
Advanced Mode
Rev.6.00 Oct.28.2004 page 123 of 1016
REJ09B0138-0600H