DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 527

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

In serial reception, the SCI operates as described below.
[1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts
[2] The received data is stored in RSR in LSB-to-MSB order.
[3] The parity bit and stop bit are received.
Note: * Subsequent receive operations cannot be performed when a receive error has occurred.
[4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is
reception.
After receiving these bits, the SCI carries out the following checks.
[a] Parity check:
[b] Stop bit check:
[c] Status check:
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR.
If a receive error* is detected in the error check, the operation is as shown in table 14-11.
generated.
Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI)
request is generated.
The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E
bit in SMR.
The SCI checks whether the stop bit is 1.
If there are two stop bits, only the first is checked.
The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR.
Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0.
Rev.6.00 Oct.28.2004 page 497 of 1016
REJ09B0138-0600H