DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 467

IC H8S MCU FLASH 256K 120TQFP

DF2398TE20

Manufacturer Part Number
DF2398TE20
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2398TE20

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2398TE20
HD64F2398TE20

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12.2.3
TCORB0 and TCORB1 are 8-bit readable/writable registers. TCORB0 and TCORB1 comprise a single 16-bit register so
they can be accessed together by word transfer instruction.
TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag of
TCSR is set. Note, however, that comparison is disabled during the T
The timer output can be freely controlled by these compare match signals and the settings of output select bits OS3 and
OS2 of TCSR.
TCORB0 and TCORB1 are each initialized to H'FF by a reset and in hardware standby mode.
12.2.4
TCR0 and TCR1 are 8-bit readable/writable registers that select the clock source and the time at which TCNT is cleared,
and enable interrupts.
TCR0 and TCR1 are each initialized to H'00 by a reset and in hardware standby mode.
For details of this timing, see section 12.3, Operation.
Bit 7—Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt requests (CMIB) are enabled
or disabled when the CMFB flag of TCSR is set to 1.
Bit 6—Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt requests (CMIA) are enabled
or disabled when the CMFA flag of TCSR is set to 1.
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Time Constant Registers B0 and B1 (TCORB0, TCORB1)
Time Control Registers 0 and 1 (TCR0, TCR1)
Bit 7
CMIEB
0
1
Bit 6
CMIEA
0
1
:
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
:
:
15
CMIEB
1
R/W
7
0
14
1
Description
CMFB interrupt requests (CMIB) are disabled
CMFB interrupt requests (CMIB) are enabled
Description
CMFA interrupt requests (CMIA) are disabled
CMFA interrupt requests (CMIA) are enabled
13
CMIEA
1
R/W
6
0
TCORB0
12
1
11
1
OVIE
R/W
5
0
10
1
CCLR1
9
1
R/W
4
0
8
1
CCLR0
7
1
R/W
3
0
6
1
2
5
1
CKS2
R/W
state of a TCOR write cycle.
2
0
TCORB1
4
1
3
1
CKS1
R/W
Rev.6.00 Oct.28.2004 page 437 of 1016
1
0
2
1
1
1
CKS0
R/W
0
0
0
1
(Initial value)
(Initial value)
REJ09B0138-0600H

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