DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 106
DF2398TE20
Manufacturer Part Number
DF2398TE20
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2398TE20
HD64F2398TE20
HD64F2398TE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 106 of 1049
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4.2.4
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved
correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after
a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that
this instruction initializes the stack pointer (example: MOV.L #xx:32, SP).
4.2.5
After reset release, MSTPCR is initialized to H'3FFF and all modules except the DMAC and DTC enter module stop
mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is
enabled when module stop mode is exited.
4.3
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the
state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each
instruction.
Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking.
Table 4-4 shows the state of CCR and EXR after execution of trace exception handling.
Interrupts are accepted even within the trace exception handling routine.
The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine
by the RTE instruction, trace mode resumes.
Trace exception handling is not carried out after execution of the RTE instruction.
Table 4-4
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
Rev.6.00 Oct.28.2004 page 76 of 1016
REJ09B0138-0600H
Interrupts after Reset
State of On-Chip Supporting Modules after Reset Release
Traces
Interrupt Control Mode
0
2
Status of CCR and EXR after Trace Exception Handling
I
1
Trace exception handling cannot be used.
CCR
UI
—
I2 to I0
—
EXR
T
0
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