DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 506

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception
Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal
termination.
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing
abnormal termination.
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
Rev.6.00 Oct.28.2004 page 476 of 1016
REJ09B0138-0600H
or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the
receive data will be lost.
2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also,
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a
subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode,
serial transmission cannot be continued, either.
framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent
serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial
transmission cannot be continued, either.
Bit 6
RDRF
0
1
Bit 5
ORER
0
1
Bit 4
FER
0
1
Description
[Clearing conditions]
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Description
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1*
Description
[Clearing condition]
When 0 is written to FER after reading FER = 1
[Setting condition]
When the SCI checks whether the stop bit at the end of the receive data when
reception ends, and the stop bit is 0 *
When 0 is written to RDRF after reading RDRF = 1
When the DMAC or DTC is activated by an RXI interrupt and read data from RDR
2
2
(Initial value)*
(Initial value)*
(Initial value)
1
1