DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 174

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

6.5.10
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each
access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same
row address. This mode enables fast (burst) access of data by simply changing the column address after the row address
has been output. Burst access can be selected by setting the BE bit in MCR to 1.
Burst Access (Fast Page Mode) Operation Timing: Figure 6-20 shows the operation timing for burst access. When
there are consecutive access cycles for DRAM space, the CAS signal and column address output cycles (two states)
continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is
set with bits MXC1 and MXC0 in MCR.
The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are
the same as for full access. For details, see section 6.5.8, Wait Control.
Rev.6.00 Oct.28.2004 page 144 of 1016
REJ09B0138-0600H
Burst Operation
Read
Write
Note: n = 2 to 5
CSn, (RAS)
CAS, LCAS
HWR, (WE)
HWR, (WE)
D
D
A
15
15
23
to A
to D
to D
Figure 6-20 Operation Timing in Fast Page Mode
ø
0
0
0
T
p
Row
T
r
T
c1
Column1
T
c2
T
c1
Column2
T
c2