DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 397

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

Bits 7 and 6—Reserved: Should always be written with 0.
Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for TCNT.
Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the
10.2.9
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0
to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
TSYR is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 and 6—Reserved: Should always be written with 0.
Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is independent of or
synchronized with other channels.
When synchronous operation is selected, synchronous presetting of multiple channels*
counter clearing on another channel*
Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.
Bit
Initial value :
R/W
TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin
output level will be changed to the set initial output value.
2. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means
Timer Synchro Register (TSYR)
of bits CCLR2 to CCLR0 in TCR.
Bit n
CSTn
0
1
Bit n
SYNCn
0
1
:
:
—
—
7
0
Description
TCNTn count operation is stopped
TCNTn performs count operation
Description
TCNTn operates independently (TCNT presetting/clearing is unrelated to
other channels)
TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing is possible
—
—
6
0
2
are possible.
SYNC5
R/W
5
0
SYNC4
R/W
4
0
SYNC3
R/W
3
0
SYNC2
R/W
2
0
SYNC1
R/W
Rev.6.00 Oct.28.2004 page 367 of 1016
1
0
1
, and synchronous clearing through
SYNC0
R/W
0
0
(Initial value)
(Initial value)
REJ09B0138-0600H
n = 5 to 0
n = 5 to 0