DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 552

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

15.2.3
Note: * When the Smart Card interface is used, be sure to make the 0 or 1 setting shown for bits 6, 5, 3, and 2.
The function of bit 7 of SMR changes in Smart Card interface mode.
Bit 7—GSM Mode (GM): Sets the Smart Card interface function to GSM mode.
This bit is cleared to 0 when the normal Smart Card interface is used. In GSM mode, this bit is set to 1, the timing of
setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is
performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control
register (SCR).
Note: etu: Elementary time unit (time for transfer of 1 bit)
Bits 6 to 0—Operate in the same way as for the normal SCI.
For details, see section 14.2.5, Serial Mode Register (SMR).
Rev.6.00 Oct.28.2004 page 522 of 1016
REJ09B0138-0600H
Bit
Initial value :
Set value* :
R/W
Serial Mode Register (SMR)
Bit 7
GM
0
1
:
:
R/W
GM
GM
7
0
Description
Normal Smart Card interface mode operation
GSM mode Smart Card interface mode operation
TEND flag generation 12.5 etu after beginning of start bit
Clock output ON/OFF control only
TEND flag generation 11.0 etu after beginning of start bit
High/low fixing control possible in addition to clock output ON/OFF control (set by
SCR)
CHR
R/W
6
0
0
R/W
PE
5
0
1
R/W
O/E
O/E
4
0
STOP
R/W
3
0
1
R/W
MP
2
0
0
CKS1
CKS1
R/W
1
0
CKS0
CKS0
R/W
0
0
(Initial value)