DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 663
![IC H8S MCU FLASH 256K 120TQFP](/photos/28/61/286120/120-tqfp_sml.jpg)
DF2398TE20
Manufacturer Part Number
DF2398TE20
Description
IC H8S MCU FLASH 256K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2398TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2398TE20
HD64F2398TE20
HD64F2398TE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2398TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 663 of 1049
- Download datasheet (5Mb)
19.17.1 Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The
channel 1 SCI to be used is set to asynchronous mode.
When a reset-start is executed after the H8S/2398 F-ZTAT chip’s pins have been set to boot mode, the boot program built
into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the
SCI. In the chip, the programming control program received via the SCI is written into the programming control program
area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control
program area and the programming control program execution state is entered (flash memory programming is performed).
The transferred programming control program must therefore include coding that follows the programming algorithm
given later.
The system configuration in boot mode is shown in figure 19-43, and the boot program mode execution procedure in
figure 19-44.
Host
Figure 19-43 System Configuration in Boot Mode
Verify data transmission
Write data reception
Chip
RxD1
TxD1
SCI1
Rev.6.00 Oct.28.2004 page 633 of 1016
Flash memory
On-chip RAM
REJ09B0138-0600H
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