DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 332

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

9.8.2
Table 9-13 shows the port A register configuration.
Table 9-13 Port A Registers
Notes: 1. Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port A. PADDR
cannot be read; if it is, an undefined value will be read.
PADDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their
output state or become high-impedance when a transition is made to software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Rev.6.00 Oct.28.2004 page 302 of 1016
REJ09B0138-0600H
Bit
Initial value :
R/W
Mode 7
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin
an input port.
Mode 6
Setting a PADDR bit to 1 makes the corresponding port A pin an address output while clearing the bit to 0 makes the
pin an input port.
Modes 4 and 5
The corresponding port A pins are address outputs irrespective of the value of bits PA4DDR to PA0DDR.
Setting one of bits PA7DDR to PA5DDR to 1 makes the corresponding port A pin an address output, while clearing
the bit to 0 makes the pin an input port.
2. PAPCR and PAODR settings are prohibited in the ROMless version.
Register Configuration
Name
Port A data direction register
Port A data register
Port A register
Port A MOS pull-up control register*
Port A open-drain control register*
:
:
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
W
7
0
W
6
0
W
5
0
2
2
Abbreviation
PADDR
PADR
PORTA
PAPCR
PAODR
W
4
0
W
3
0
R/W
W
R/W
R
R/W
R/W
W
2
0
Initial Value
H'00
H'00
Undefined
H'00
H'00
W
1
0
W
0
0
Address*
H'FEB9
H'FF69
H'FF59
H'FF70
H'FF77
1