DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 183

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

6.8
6.8.1
When the H8S/2357 Group accesses external space, it can insert a 1-state idle cycle (T
following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle
occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions
between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on.
(1) Consecutive Reads between Different Areas
If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the
start of the second read cycle. This is enabled in advanced mode.
Figure 6-31 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a
long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b),
an idle cycle is inserted, and a data collision is prevented.
Idle Cycle
Operation
Address bus
CS (area A)
CS (area B)
Data bus
RD
ø
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
T
Figure 6-31 Example of Idle Cycle Operation (1)
2
T
Long output
floating time
3
Bus cycle B
T
1
T
2
Data
collision
Address bus
CS (area A)
CS (area B)
Data bus
RD
ø
T
1
(b) Idle cycle inserted
Bus cycle A
(Initial value ICIS1 = 1)
T
Rev.6.00 Oct.28.2004 page 153 of 1016
2
I
) between bus cycles in the
T
3
T
Bus cycle B
I
T
1
REJ09B0138-0600H
T
2