DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 270

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining
from the end of the previous transfer, etc.
Internal Interrupt after End of Transfer: When the DTE bit is cleared to 0 by the end of transfer or an abort, the
selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1.
Also, if internal DMAC activation has already been initiated when operation is aborted, the transfer is executed but flag
clearing is not performed for the selected internal interrupt even if DTA is set to 1.
An internal interrupt request following the end of transfer or an abort should be handled by the CPU as necessary.
Channel Re-Setting: To reactivate a number of channels when multiple channels are enabled, use exclusive handling of
transfer end interrupts, and perform DMABCR control bit operations exclusively.
Note, in particular, that in cases where multiple interrupts are generated between reading and writing of DMABCR, and a
DMABCR operation is performed during new interrupt handling, the DMABCR write data in the original interrupt
handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts.
Ensure that overlapping DMABCR operations are not performed by multiple interrupts, and that there is no separation
between read and write operations by the use of a bit-manipulation instruction.
Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must first be read while cleared
to 0 before the CPU can write 1 to them.
Rev.6.00 Oct.28.2004 page 240 of 1016
REJ09B0138-0600H