DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 705

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

21.6
21.6.1
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this
mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers,
RAM data, and the states of on-chip supporting modules other than the SCI and A/D converter, and I/O ports, are retained.
Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be
specified by the OPE bit in SBYCR.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
21.6.2
Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ2), or by means of the RES pin
or STBY pin.
21.6.3
Bits STS2 to STS0 in SBYCR should be set as described below.
Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization
time).
Clearing with an interrupt
When an NMI or IRQ0 to IRQ2 interrupt request signal is input, clock oscillation starts, and after the elapse of the time
set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire H8S/2357 Group chip, software standby
mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ2 interrupt, set the corresponding enable bit to 1 and
ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ2 is generated. Software standby mode
cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source.
Clearing with the RES pin
When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are
supplied to the entire H8S/2357 Group chip. Note that the RES pin must be held low until clock oscillation stabilizes.
When the RES pin goes high, the CPU begins reset exception handling.
Clearing with the STBY pin
When the STBY pin is driven low, a transition is made to hardware standby mode.
Software Standby Mode
Software Standby Mode
Clearing Software Standby Mode
Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Rev.6.00 Oct.28.2004 page 675 of 1016
REJ09B0138-0600H