DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 144

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst
access.
Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 to 5 in advanced
mode.
When DRAM space is selected, the relevant area is designated as DRAM interface.
Note: When areas selected in DRAM space are all 8-bit space, the PF
6.2.5
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, the LCAS
signal, DMAC single address transfer, enabling or disabling of the write data buffer function, and enabling or disabling of
WAIT pin input.
BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or
in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Rev.6.00 Oct.28.2004 page 114 of 1016
REJ09B0138-0600H
Bit
Initial value :
R/W
Bus Control Register L (BCRL)
Bit 3
BRSTS0
0
1
Bit 7
BRLE
0
1
Bit 2
RMTS2
0
1
:
:
BRLE
R/W
7
0
Description
Max. 4 words in burst access
Max. 8 words in burst access
Bit 1
RMTS1
0
1
—
Description
External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O ports.
External bus release is enabled.
BREQOE
R/W
6
0
Bit 0
RMTS0
0
1
0
1
—
EAE
R/W
5
1
Description
Area 5
Normal space
Normal space
Normal space
DRAM space
—
LCASS
R/W
4
1
DDS
R/W
3
1
Area 4
2
R/W
—
pin can be used as an I/O port, BREQO, or WAIT.
2
1
WDBE
Area 3
DRAM space
R/W
1
0
WAITE
R/W
0
0
Area 2
DRAM space
(Initial value)
(Initial value)