DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 123

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

(3) Default Priority Determination
When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated.
If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the
highest priority according to the preset default priorities is selected and has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5-8 shows operations and control signal functions in each interrupt control mode.
Table 5-8
Legend
IM: Used as interrupt mask bit
PR: Sets priority
—: Not used
Notes: 1. Set to 1 when interrupt is accepted.
5.4.2
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the
CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1.
Figure 5-5 shows a flowchart of the interrupt acceptance operation in this case.
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the
[2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an
[3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is
[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has
[5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the
[6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
[7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the
:
: Interrupt operation control performed
interrupt controller.
NMI interrupt is accepted, and other interrupt requests are held pending.
accepted, and other interrupt requests are held pending.
been completed.
address of the first instruction to be executed after returning from the interrupt handling routine.
address indicated by the contents of that vector address.
No operation. (All interrupts enabled)
2. Keep the initial setting.
Interrupt Control Mode 0
Interrupt
Control Setting
Mode
0
2
Operations and Control Signal Functions in Each Interrupt Control Mode
INTM1 INTM0
0
1
0
0
Interrupt
Acceptance Control
I
—*
IM
1
I2 to I0
8-Level Control
—
IM
IPR
—*
PR
2
Rev.6.00 Oct.28.2004 page 93 of 1016
Default
Priority
Determination
T
(Trace)
—
T
REJ09B0138-0600H