DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 184

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

(2) Write after Read
If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the
start of the write cycle.
Figure 6-32 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a
long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs
in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is
prevented.
Rev.6.00 Oct.28.2004 page 154 of 1016
REJ09B0138-0600H
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
ø
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS0 = 0)
T
Figure 6-32 Example of Idle Cycle Operation (2)
2
T
floating time
Long output
3
Bus cycle B
T
1
T
2
Data
collision
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
ø
T
(b) Idle cycle inserted
1
Bus cycle A
(Initial value ICIS0 = 1)
T
2
T
3
T
I
Bus cycle B
T
1
T
2