DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 195

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

7.1
The H8S/2357 Group has a on-chip DMA controller (DMAC) which can carry out data transfer on up to 4 channels.
7.1.1
The features of the DMAC are listed below.
Choice of short address mode or full address mode
Short address mode
Full address mode
16-Mbyte address space can be specified directly
Byte or word can be set as the transfer unit
Activation sources: internal interrupt, external request, auto-request (depending on transfer mode)
Module stop mode can be set
Maximum of 4 channels can be used
Choice of dual address mode or single address mode
In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and
In single address mode, transfer source or transfer destination address only is specified as 24 bits
In single address mode, transfer can be performed in one bus cycle
Choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode
Maximum of 2 channels can be used
Transfer source and transfer destination address specified as 24 bits
Choice of normal mode or block transfer mode
Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts
Serial communication interface (SCI0, SCI1) transmission data empty interrupt, reception data full interrupt
A/D converter conversion end interrupt
External request
Auto-request
The initial setting enables DMAC registers to be accessed. DMAC operation is halted by setting module stop mode
the other as 16 bits
Overview
Features
Section 7 DMA Controller
Rev.6.00 Oct.28.2004 page 165 of 1016
REJ09B0138-0600H