DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 463

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

12.1
The H8S/2357 Group includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit
counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT
value to detect compare match events. The 8-bit timer module can thus be used for a variety of functions, including pulse
output with an arbitrary duty cycle.
12.1.1
The features of the 8-bit timer module are listed below.
Selection of four clock sources
The counters can be driven by one of three internal clock signals (ø/8, ø/64, or ø/8192) or an external clock input
(enabling use as an external event counter).
Selection of three ways to clear the counters
The counters can be cleared on compare match A or B, or by an external reset signal.
Timer output control by a combination of two compare match signals
The timer output signal in each channel is controlled by a combination of two independent compare match signals,
enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output.
Provision for cascading of two channels
Three independent interrupts
Compare match A and B and overflow interrupts can be requested independently.
A/D converter conversion start trigger can be generated
Channel 0 compare match A signal can be used as an A/D converter conversion start trigger.
Module stop mode can be set
Operation as a 16-bit timer is possible, using channel 0 for the upper 8 bits and channel 1 for the lower 8 bits (16-
Channel 1 can be used to count channel 0 compare matches (compare match count mode).
bit count mode).
As the initial setting, 8-bit timer operation is halted. Register access is enabled by exiting module stop mode.
Overview
Features
Section 12 8-Bit Timers
Rev.6.00 Oct.28.2004 page 433 of 1016
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