DF2398TE20 Renesas Electronics America, DF2398TE20 Datasheet - Page 220

• Manufacturer Part Number: DF2398TE20
• Description: IC H8S MCU FLASH 256K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2398TE20; HD64F2398TE20

7.4
7.4.1
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a
DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that specific bits of DMACR for the
specific channel, and also DMATCR and DMABCR, can be changed to prevent inadvertent rewriting of registers other
than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC.
Figure 7-2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt, and reactivating
channel 0A. The address register and count register area is re-set by the first DTC transfer, then the control register area is
re-set by the second DTC chain transfer.
When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the
contents of the other channels.
DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the DMACR, DMABCR,
and DMATCR by the DTC.
DMAWER is initialized to H'00 by a reset, and in standby mode.
Rev.6.00 Oct.28.2004 page 190 of 1016
REJ09B0138-0600H
Bit
DMAWER :
Initial value :
R/W
Register Descriptions (3)
DMA Write Enable Register (DMAWER)
:
:
—
—
7
0
Figure 7-2 Areas for Register Re-Setting by DTC (Example: Channel 0A)
—
—
6
0
DTC
—
—
5
0
Second transfer area
using chain transfer
—
—
First transfer area
4
0
WE1B
R/W
3
0
WE1A
DMACR0A
DMACR1A
DMAWER
R/W
2
0
DMABCR
ETCR0A
ETCR0B
ETCR1A
ETCR1B
IOAR0A
IOAR0B
IOAR1A
IOAR1B
MAR0A
MAR0B
MAR1A
MAR1B
WE0B
DMACR0B
DMACR1B
R/W
DMATCR
1
0
WE0A
R/W
0
0